Some ICs include through silicon vias (TSVs) which are also referred to as through wafer vias (TWS). Due to their considerably shorter length as compared to conventional wire bond connections, TSVs reduce inductance and resistance and thus improve IC performance.
As known in the art of semiconductor package assembly, in conventional assembly processing for ICs that comprise TSVs, solder regions are applied to the workpiece which can comprise a package substrate (e.g. printed circuit board (PCB)) or other IC die. The IC is aligned such that the TSV tips are aligned to the solder regions, followed by attachment to the workpiece. Underfill is then generally applied after attachment.